single-pll general-purpose eprom programmable clock generato r cy2071a cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07139 rev. *d revised august 3, 2006 features ? single phase-locked loop architecture ? eprom programmability ? factory-programmable (cy2071a, cy2071ai) or field-programmable (cy2071af, cy2071afi) device options ? up to three configurable outputs ? low skew, low jitter, high-accuracy outputs ? internal loop filter ? power management (oe) ? frequency select options ? configurable 5v or 3.3v operation ? 8-pin 150-mil soic package benefits ? generates a custom frequency from an external source ? easy customization and fast turnaround ? programming support available for all opportunities ? generates three related frequencies from a single device ? meets critical industry standard timing requirements ? alleviates the need for external components ? supports low-power applications ? three outputs with two user-selectable frequencies ? supports industry standard design platforms ? industry standard packaging saves on board space selector guide part number outputs input frequency range output frequency range specifics cy2071a 3 10 mhz?25 mhz (external crystal) 1 mhz?30 mhz (reference clock) 500 khz?130 mhz (5v) 500 khz?100 mhz (3.3v) factory programmable commercial temperature cy2071ai 3 10 mhz?25 mhz (external crystal) 1 mhz?30 mhz (reference clock) 500 khz?100 mhz (5v) 500 khz?80 mhz (3.3v) factory programmable industrial temperature cy2071af 3 10 mhz?25 mhz (external crystal) 1 mhz?30 mhz (reference clock) 500 khz?100 mhz (5v) 500 khz?80 mhz (3.3v) field programmable commercial temperature cy2071afi 3 10 mhz?25 mhz (external crystal) 1 mhz?30 mhz (reference clock) 500 khz?90 mhz (5v) 500 khz?66.6 mhz (3.3v) field programmable industrial temperature 1 2 3 4 5 8 7 6 clka gnd xtalin xtalout v dd oe/fs clkc clkb xtalout xtalin reference oscillator pll block clka clkb clkc eprom- configurable multiplexer and divide logic oe / fs logic block diagram for cy2071a top view 8-pin soic pin configuration [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 2 of 9 functional description the cy2071a is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, cd-rom drives, video cd players, games, set-top boxes, and data/telecommunications. the device offers up to three config- urable clock outputs in an 8-pin, 150-mil soic package and can operate off either a 3.3v or 5v power supply. the on-chip reference oscillator is designed for 10 mhz to 25 mhz crystals. alternatively, an external reference clock of frequency between 1 mhz and 30 mhz can be used. the cy2071a has one pll and outputs three factory-eprom configurable clocks: clka, clkb, and clkc. the output clocks can originate either from the pll or the reference, or selected dividers thereof. additionally, pin 8 can be configured to be an output enable or a select input. the cy2071a can replace mult iple metal can oscillators (mco) in a synchronous system, providing cost and board space savings to the manufacturer. hence, these devices are ideally suited for applications t hat require multiple, accurate, and stable clocks synthesized fr om low-cost generators in small packages. a hard-disk drive is an example of such an application. in this case, clka drives the pll in the read controller, while clkb and clkc drive the mcu and associated sequencers. cyclocks software cyclocks ? is an easy-to-use software application that allows you to configure any one of the eprom-programmable clocks offered by cypress. you may specify the input frequency, pll and output frequencies, and different functional options. note the output frequency ranges in this data sheet when specifying th em in cyclocks to ensure that you stay within the limits. you can download a copy of cyclocks free on the cypress semiconductor corporation web site at www.cypress.com. use the cy2081 for applications that require unrelated output frequencies. use the cy2291, cy2292, or cy2907 for appli- cations that require more than three output clocks. cypress ftg programmer the cypress frequency timing generator (ftg) programmer is a portable programmer designed to custom program our family of eprom field programmable clock devices. the ftg programmers connect to a pc serial port and allow users of cyclocks software to easily program any of the cy2291f, cy2292f, cy2071af, and cy2907f devices. the ordering code for the cypress ftg programmer is cy3670. notes 1. for best accuracy, use a parallel-resonant crystal, c l = 17 pf. 2. float xtalout pin if xtalin is driven by refe rence clock (as opposed to an external crystal). 3. stresses greater than those listed in this table may cause permanent damage to the device. 4. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. pin summary name number description clka 1 configurable clock output gnd 2 ground xtalin [1] 3 reference crystal input or external reference clock input xtalout [1, 2] 4 reference crystal feedback clkb 5 configurable clock output clkc 6 configurable clock output v dd 7 voltage supply oe / fs 8 output control pin, eit her output enable or frequency select input (active high, internal pull-up resistor to v dd ) absolute maximum conditions [3, 4] parameter description condition min. max. unit v dd analog supply voltage ?0.5 7.0 v v in dc input voltage ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 150 c t a temperature, maximum soldering (10 sec) functional ? 260 c t j temperature, junction functional ? 150 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 3 of 9 notes: 5. electrical parameters are guaranteed with these operating c onditions. values for 3.3v operation are shown in parentheses. 6. external input reference clock must have a duty cycle between 40% and 60%, measured at v dd /2. 7. please refer to application note ?crystal oscillator topics? for information on ac-coupling the external input reference cloc k. 8. see ?cy2071a and cy2907 clock generators? applicat ion note for important customer clarification. 9. xtal inputs have cmos thresholds. 10. load = max, typical configuration, f ref = 14.318 mhz. specific configurations may vary. a close approximation of i dd can be derived by the following formula: i dd (ma) = v dd *(6.25+(0.055*f ref ) + (0.0017*c load *(f clka +f clkb +f clkc ))). c load is specified in pf a nd f is specified in mhz. operating conditions [5] parameter description min. max. unit v dd supply voltage, 5.0v operation 4.5 5.5 v v dd supply voltage, 3.3v operation 3.0 3.6 v t a commercial operating temp erature, ambient 0 70 c industrial operating temp erature, ambient ?40 85 c c l max. load capacitance per output (5v operation) ? 25 pf max. load capacitance per output (3.3v operation) ? 15 pf f ref external reference crystal 10.0 25.0 mhz external reference clock [6, 7] 1.0 30.0 mhz t pu power-up time for all vdds to reach mi nimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics, commercial 5.0v: v dd = 5v 10%, t a = 0c to +70c [8] parameter description conditions min. typ. max. unit v oh high-level output voltage i oh = ?4.0 ma 2.4 ? ? v v ol low-level output voltage i ol = 4.0 ma ? ? 0.4 v v ih high-level input voltage [9] except crystal pins 2.0 ? ? v v il low-level output voltage [9] except crystal pins ? ? 0.8 v i ih input high current v in = v dd ? 0.5v ? ? 10 a i il input low current v in = 0.5v ? ? 150 a i oz output leakage current three state outputs ? ? 250 a i dd v dd supply current [10] v dd = v dd max. 5v operation, c l = 25 pf 40 60 ma electrical characteristics, commercial 3.3v: v dd = 3.3v 10%, t a = 0 c to 70 c [8] parameter description conditions min. typ. max. unit v oh high-level output voltage i oh = ?4.0 ma 2.4 ? ? v v ol low-level output voltage i ol = 4.0 ma ? ? 0.4 v v ih high-level input voltage [9] except crystal pins 2.0 ? ? v v il low-level output voltage [9] except crystal pins ? ? 0.8 v i ih input high current v in = v dd ? 0.5v ? ? 10 a i il input low current v in = 0.5v ? ? 150 a i oz output leakage current three state outputs ? ? 250 a i dd v dd supply current [10] v dd = v dd max. 3.3v operation, c l = 15 pf ? 24 40 ma [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 4 of 9 electrical characteristics, industrial 5.0v: v dd = 5.0v 10%, t a = ?40c to 85c [8] parameter description conditions min. typ. max. unit v oh high-level output voltage i oh = ?4.0 ma 2.4 v v ol low-level output voltage i ol = 4.0 ma 0.4 v v ih high-level input voltage [9] except crystal pins 2.0 v v il low-level output voltage [9] except crystal pins 0.8 v i ih input high current v in = v dd ? 0.5v 10 a i il input low current v in = 0.5v 150 a i oz output leakage current three state outputs 250 a i dd v dd supply current [10] v dd = v dd max. 5v operation, c l = 25 pf 40 75 ma electrical characteristics, industrial 3.3v v dd =3.3v 10%, t a = ?40c to +85c [8] parameter description conditions min. typ. max. unit v oh high-level output voltage i oh = ?4.0 ma 2.4 v v ol low-level output voltage i ol = 4.0 ma 0.4 v v ih high-level input voltage [9] except crystal pins 2.0 v v il low-level output voltage [9] except crystal pins 0.8 v i ih input high current v in = v dd ? 0.5v 10 a i il input low current v in = 0.5v 150 a i oz output leakage current three state outputs 250 a i dd v dd supply current [10] v dd = v dd max. 3.3v operation, c l = 15 pf 24 50 ma notes: 11. guaranteed by design, not 100% tested. 12. when the output clock frequency is between 100 mhz and 130 mhz at 5v, the maximum capacitive load for these measurements is 15 pf. 13. reference output duty cycle depends on xtalin duty cycle. 14. measured at 1.4v. switching characteristics, commercial 5.0v [11] parameter name description min. typ. max. unit t 1 output period clock output range 5v operation 25-pf load cy2071a 7.692 [130 mhz] 2000 [500 khz] ns cy2071af 10 [100 mhz] 2000 [500 khz] ns t 1a clock jitter peak-to-peak period jitter (t 1 max. ? t 1 min.), % of clock period, f out 16 mhz 0.8 1 % t 1b clock jitter peak-to-peak period jitter (16 mhz f out 50 mhz) 350 500 ps t 1c clock jitter [12] peak-to-peak period jitter (f out > 50 mhz) 250 350 ps output duty cycle duty cycle [13, 14] for outputs, (t 2 t 1 ) f out 60 mhz 45% 50% 55% output duty cycle [12] duty cycle [14] for outputs, (t 2 t 1 ), f out > 60 mhz 40% 50% 60% t 3 rise time [12] output clock rise time 1.5 2.5 ns t 4 fall time [12] output clock fall time 1.5 2.5 ns t 5 skew skew delay between any two outputs with identical frequencies (generated by the pll) 0.5 ns [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 5 of 9 switching characteristics, commercial 3.3v [11] parameter name description min. typ. max. unit t 1 output period clock output range 3.3v operation 15-pf load cy2071as 10 [100 mhz] 2000 [500 khz] ns cy2071af 12.50 [80 mhz] 2000 [500 khz] ns t 1a clock jitter peak-to-peak period jitter (t 1 max. ? t 1 min.), % of clock period, f out 16 mhz 0.8 1 % t 1b clock jitter peak-to-peak period jitter (16 mhz f out 50 mhz) 350 500 ps t 1c clock jitter [12] peak-to-peak period jitter (f out > 50 mhz) 250 350 ps output duty cycle duty cycle [13, 14] for outputs, (t 2 t 1 ) f out 60 mhz 45% 50% 55% output duty cycle [12] duty cycle [14] for outputs, (t 2 t 1 ), f out > 60 mhz 40% 50% 60% t 3 rise time [12] output clock rise time 1.5 2.5 ns t 4 fall time [12] output clock fall time 1.5 2.5 ns t 5 skew skew delay between any two outputs with identical frequencies (generated by the pll) 0.5 ns switching characteristics, industrial 5.0v [11] parameter name description min. typ. max. unit t 1 output period clock out put range 5.0v operation 25-pf load cy2071ai 10 [100 mhz] 2000 [500 khz] ns cy2071afi 11.1 [90 mhz] 2000 [500 khz] ns t 1a clock jitter peak-to-peak period jitter (t 1 max. ? t 1 min.), % of clock period, f out 16 mhz 0.8 1 % t 1b clock jitter peak-to-pe ak period jitter (16 mhz f out 50 mhz) 350 500 ps t 1c clock jitter [12] peak-to-peak period jitter (f out > 50 mhz) 250 350 ps output duty cycle duty cycle [13, 14] for outputs, (t 2 t 1 ) f out 60 mhz 45% 50% 55% output duty cycle [12] duty cycle [14] for outputs, (t 2 t 1 ), f out > 60 mhz 40% 50% 60% t 3 rise time [12] output clock rise time 1.5 2.5 ns t 4 fall time [12] output clock fall time 1.5 2.5 ns t 5 skew skew delay between any two outputs with identical frequencies (generated by the pll) 0.5 ns [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 6 of 9 switching characteristics, industrial 3.3v [11] parameter name description min. typ. max. unit t 1 output period clock output range 3.3v operation 15-pf load cy2071ai 12.50 [80 mhz] 2000 [500 khz] ns cy2071afi 15.0 [66.6 mhz] 2000 [500 khz] ns t 1a clock jitter peak-to-peak period jitter (t 1 max. ? t 1 min.), % of clock period, f out 16 mhz 0.8 1 % t 1b clock jitter peak-to-peak period jitter (16 mhz f out 50 mhz) 350 500 ps t 1c clock jitter [12] peak-to-peak period jitter (f out > 50 mhz) 250 350 ps output duty cycle duty cycle [13, 14] for outputs, (t 2 t 1 ) f out 60 mhz 45% 50% 55% output duty cy- cle [12] duty cycle [14] for outputs, (t 2 t 1 ), f out > 60 mhz 40% 50% 60% t 3 rise time [12] output clock rise time 1.5 2.5 ns t 4 fall time [12] output clock fall time 1.5 2.5 ns t 5 skew skew delay between any two outputs with identi- cal frequencies (generated by the pll) 0.5 ns switching waveforms figure 1. all outputs duty cycle and rise/fall time figure 2. output-output clock skew test circuit output t 3 t 4 t 2 t 1 2.4v 0.4v 0.4v 2.4v v dd 0v output output t 5 0.1 f v dd clk output c load gnd 7 2 outputs [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 7 of 9 ordering information ordering code package type operating range cy2071asc-xxx 8-pin (150-mil) soic 5.0v, commercial, factory programmable cy2071asc-xxxt 8-pin (150-mil) soic ? tape and reel 5.0v, commercial, factory programmable cy2071asl-xxx 8-pin (150-mil) soic 3.3v, commercial, factory programmable cy2071asl-xxxt 8-pin (150-mil) soic ? tape and reel 3.3v, commercial, factory programmable CY2071ASI-XXX 8-pin (150-mil) soic 5v/3.3v, industrial, factory programmable CY2071ASI-XXXt 8-pin (150-mil) soic ? tape and reel 5v/3.3v, industrial, factory programmable cy2071af 8-pin (150-mil) soic 5v/3.3 v, commercial, field programmable cy2071aft 8-pin (150-mil) soic ? tape and reel 5v/3.3v, commercial, field programmable cy2071afi 8-pin (150-mil) soic 5v/3.3v, industrial, field programmable cy2071afit 8-pin (150-mil) soic ? tape and r eel 5v/3.3v, industrial, field programmable cy3670 ftg programmer custom programming for field programmable clocks lead-free cy2071asxc-xxx 8-pin (150-mil) soic 5.0v , commercial, factory programmable cy2071asxc-xxxt 8-pin (150-mil) soic - tape and reel 5.0v, commercial, factory programmable cy2071asxl-xxx 8-pin (150-mil) soic 3.3v , commercial, factory programmable cy2071asxl-xxxt 8-pin (150-mil) soic- tape and reel 3.3v, comm ercial, factory programmable cy2071asxi-xxx 8-pin (150-mil) soic 5v/3.3v, industrial, factory programmable cy2071asxi-xxxt 8-pin (150-mil) soic- tape and reel 5v/3.3v, industrial, factory programmable cy2071afxc 8-pin (150-mil) soic 5v/3.3 v, commercial, field programmable cy2071afxct 8-pin (150-mil) soic- tape and reel 5v/3.3v, commercial, field programmable cy2071afxi 8-pin (150-mil) soic 5v/3.3v, industrial, field programmable cy2071afxit 8-pin (150-mil) soic- tape and reel 5v/3.3v, industrial, field programmable package characteristics package ja (c/w) jc (c/w) transistor count 8 pin soic 170 35 5436 [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions figure 3. 8-lead (150-mil) soic s8 cyclocks is a trademark of cypress semic onductor corporation. all product and co mpany names mentioned in this document are trademarks of their respective holders. seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic - s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c [+] feedback [+] feedback
cy2071a document #: 38-07139 rev. *d page 9 of 9 document history page document title: cy2071a single-pll general-purpose eprom programmable clock generator document number: 38-07139 rev. ecn no. issue date orig. of change description of change ** 110248 12/17/01 szv change from spec number: 38-00521 to 38-07139 *a 121827 12/14/02 rbi power up requirements added to operating conditions information *b 279389 see ecn rgl added lead-free devices *c 296792 see ecn rgl minor typo: missed one letter (c) in the ordering code *d 492389 see ecn rgl added a note on all electrical specs table specifying the application notes name for customer?s clarification reformatted using new template [+] feedback [+] feedback
|
